FPGAs and Deep Machine Learning


The concept of machine learning is not new. Attempts at systems emulating intelligent behavior, like expert systems, go as far back as the early 1980’s.

Three latest development are pushing forward “Machine Learning”:

  • Powerful distributed processors
  • Cheap and high volume storage
  • High bandwidth interconnection to bring the data to the processors

As in many other fields, development of Machine Learning is also seeing development on algorithms that take advantage of the new hardware capabilities.

There are four types of algorithms used in machine learning:

  • Supervised – The vast majority of systems today. These systems are ‘trained’ based on past data on an attempt to predict future outcomes.
  • Unsupervised – These systems try to build models, by themselves, of the process analyzed.
  • Semi supervised – is a combination of the first two, where a small amount of data is ‘labeled’ (i.e. related to known training rules) and the machine uses this as a seed to label the rest of the data
  • Reinforcement – The algorithm creates its rules through trial and error.

According Wikipedia, Deep Learning is “a part of a broader family of machine learning methods based on learning representations of data. An observation (e.g., an image) can be represented in many ways such as a vector of intensity values per pixel, or in a more abstract way as a set of edges, regions of particular shape, etc. Some representations are better than others at simplifying the learning task”.

Many Deep Learning solutions were based on the use of GPUs. However, FPGAs are being seen as a valid alternative for GPU based Deep Learning solutions.

The main reason for that is the lower cost and lower power consumption of FPGAs compared to GPUs in Deep Learning applications.

Microsoft adopted Altera Arria 10 devices for their Convolutional Neural Network (CNNs), estimating that the usage of FPGAs would increase their system throughput roughly at 70% with the same power consumption.

A recent article on Next Platform comments on how Baidu has also adopted FPGAs for deep learning solutions.

Teradeep is another company (startup) developing CNNs, and one among the first of those adopting FPGAs as an alternative to GPUs. In May this year Xilinx announced it invested in Teradeep and continue working closely together to optimize its technology.

For some time Altera has been pushing OpenCL for the implementation of Neural Networks. New devices from Altera and Xilinx are specifically oriented for distributed processing applications, efficient integration of FPGAs with high end processors and/or high bandwidth throughput (see our previous articles Stratix 10MX – High memory bandwidth on SiP package and Intel announces Xeon processor with FPGA accelerator)

Pseudo random generator Tutorial – Part 3

On the first two chapters of this Tutorial we started with a simple LFSR module and added a test bench. Then, on chapters three and four we upgraded our module with some features and learned to export the test bench data to files.

Chapter 5 – Matlab Formal Verification

Our VHDL block implements an algorithm that generates pseudo-random numbers. If the register is large enough, the output of the block will be hundreds or thousands of different numbers. How can we be sure that our block is working OK?

Continue reading “Pseudo random generator Tutorial – Part 3”

TI power solution for Arria 10 GX


“Field programmable gate arrays (FPGAs) are increasingly complex system on chips (SoCs) that include not just programmable logic gates and random access memory (RAM) but also analog-to-digital converters (ADCs); digital-to-analog converters (DACs); and programmable analog features and signal-conditioning circuits that enable high-performance digital computations in servers, network-attached storage (NAS), enterprise switches, oscilloscopes, network analyzers, test equipment and software-defined radios.”

Continue reading “TI power solution for Arria 10 GX”

The MicroZed chronicles – Free FPGA book


Adam Taylor is the well known author of the MicroZed Chronicles blog on Xilinx website. His Chronicles have been running for several years, and Adam has already compiled entries from his blog in two books. The first book is offered for free on the FPGARelated website for registered users.

Continue reading “The MicroZed chronicles – Free FPGA book”

Pseudo random generator Tutorial – Part 2


Modelsim Altera running an LFSR simulation

On the first part of this tutorial, we started with a simple implementation of an LFSR block (Chapter 1) and it test bench (Chapter 2). Let’s make our code a bit more professional.

Chapter 3 – Upgrading the LFSR code

Good code doesn’t use hard-coded constants as were used on the first part (to define the LFSR width). The downside of using constants is that code updates and maintenance is cumbersome at best. If we want to change the width of the register… we must scan the code and change each and every instance of the constant. There is a great possibility of making mistakes while doing that. Forgetting to change one of the ‘3’s… or changing one that was not related to the register width. This is not clearly seen in a short piece of code, but as our code gets longer, maintaining hard-coded constants is a sure recipe for trouble.

Continue reading “Pseudo random generator Tutorial – Part 2”